1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a conductive layer.
2. Description of Related Art
As a line width of a semiconductor device is gradually minimized, the distance between two neighboring conductive lines is gradually reduced. However, the shorter the distance between the two neighboring conductive lines is, the more serious a parasitic capacitor effect is. A parasitic capacitor is generated between the two neighboring conductive lines. A parasitic capacitor effect is affected by a dielectric constant of the dielectric layer and a distance between the two neighboring conductive lines. Consequently, a high dielectric constant and a small distance between the two neighboring conductive lines both easily cause a parasitic capacitor. When the parasitic capacitor effect is serious, resistance capacitance (RC) time delay is increased so as to decrease transferring speed in integrated circuits.
FIG. 1 is a schematic, cross-sectional view of a conductive line.
Referring to FIG. 1, a metallic layer (not shown) is formed on a semiconductor substrate 100. A photoresist layer (not shown) having a pattern of a subsequently formed metal line is formed on the metallic layer. Two etching steps are performed on the metallic layer. Using the photoresist layer as a mask, a first etching step is performed on the metallic layer to form a metal line 102. A second etching step is performed on the metal line 102 to clean away residue generated on the substrate 100 during the first etching step. A dielectric layer 104 is formed over the substrate 100 to cover the metal line 102. An air gap 106 is commonly formed in the dielectric layer 104 between the two neighboring metal lines 102. A dielectric layer 104a including the air gap 106 and the dielectric layer 104 is formed. Since the air gap 106 exists in the dielectric layer 104, the dielectric constant of the dielectric layer 104a can be minimized.
However, the conventionally formed conductive line 102 has a tapered profile, as shown in FIG. 1. In other words, the conductive line 102 has a wider bottom than the top. Hence, a distance between the two neighboring metal lines is decreased. While forming the dielectric layer 104 on the substrate 100, the dielectric layer 104 has a better coverage ability because the conductive line 102 has a tapered profile. Consequently, the dielectric layer 104 easily fills an area between the two neighboring metal lines so that the air gap 106 becomes smaller. Thus, the air gap 106 cannot efficiently reduce the dielectric constant of the dielectric layer 104a so as to increase a parasitic capacitor induced between the two metal lines 102.
Moreover, the conventionally formed metal line 102 has a tapered profile so as to decrease a distance between the two neighboring metal lines 102. Consequently, a parasitic capacitor generated between the two metal lines 102 is also increased.